Scalable RSA Processor in Reconfigurable Hardware - a SoC Building Block

The paper introduces a scalable programmable RSA cryptographic processor implemented as IP core in Field Programmable Devices (FPD). The processor is built on three main blocks – an embedded standard microcontroller, a scalable Montgomery Multiplication unit and simple vector adder unit. All blocks are implemented in VHDL as parameterized modules. The IP core is developed as a System on a Chip (SoC) building block for public-key exchange schemes to be used in more complex cryptographic chip using both symmetrical and asymmetrical algorithms. There is no limitation on the maximum size of RSA operands and the selection of actual word-size can be made according to the available FPD capacity and/or desired performance.